Method to fabricate self-aligned source and drain in split gate flash

ABSTRACT

A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates generally to semiconductorintegrated circuit technology and more particularly to split gate memorycells used in flash EPROMs (Electrically Erasable Programmable Read OnlyMemory).

[0003] (2) Description of Prior Art

[0004] Increased performance in computers is often directly related to ahigher level of circuit integration. Tolerances play an important rolein the ability to shrink dimensions on a chip. Self-alignment ofcomponents in a device serves to reduce tolerances and thus improve thepacking density of chips. Other techniques can be important in shrinkingdevice size. A method is disclosed later in the embodiments of thepresent invention of forming self-aligned source and drain regionsthrough which a significant reduction in the split-gate flash memorycell area is possible. As is well known in the art, a split-gate flashmemory cell normally has source and drain regions that are contacted byutilizing poly plugs. Insulating layers are required as spacers toseparate these poly plugs from the floating gates and control gates ofthe cell, and this uses up area. Furthermore, because of the highvoltages required in the erase operation the spacer width cannot bedecreased without paying a penalty in reduced reliability. Eliminationof the poly plugs, as in the method disclosed by the present invention,eliminates the reliability issue, allows a reduction in cell area andfacilitates shrinking the cell size.

[0005] A method of fabricating a traditional split gate flash memorycell is presented in FIGS. 1a-1 f, where top views of the cell arepresented at successive stages of the process and in FIGS. 2a-2 f, whichshow the corresponding cross-sections. Active regions, 10, are definedon a semiconductor substrate, 2, which preferably is a siliconsubstrate, using isolating regions, such as shallow trench isolationregions, 4. An implant is performed to adjust the cell thresholdvoltage, which may be a boron implant at about 20 keV to a dose of about5E11 per sq. cm. The floating gate oxide, 6, is then formed to athickness of about 150 Angstroms, followed by deposition of a poly 1layer, 8, to a depth of about 800 Angstroms. A photoresist layer isformed and patterned to partially define the poly 1 floating gates, andafter a poly 1 etch, to achieve the shape of region 8 as shown in FIG.1a, and removal of the photoresist, the structure is as depicted inFIGS. 1a and 2 a. The traditional method continues with formation of adielectric separator between the poly 1 floating gate and poly 2 controlgate that is disposed over the dielectric separator. This dielectricseparator often consists of composite oxide/nitride/oxide (ONO) layers,with the layer thickness being about 75, 150, 30 Angstroms,respectively. There follows a deposition of about 1000 Angstroms of poly2 and then about 1500 Angstroms of nitride 1. A photoresist layer isformed and patterned to define the control gates. Etching the nitridelayer, the poly 2 layer and the ONO layer and then removing thephotoresist results in the structure depicted in FIGS. 1b and 2 b. TheONO layer, 54, provides dielectric separation between the poly 2 layer,12, which acts as a control gate or transfer gate, and the poly 1floating gate. The nitride 1 layer, 14, is required for dielectricseparation between poly 2 and subsequent poly layers. A photoresistlayer is formed and patterned, 18, to define source/drain openings, poly1 is etched and source/drain implantation performed to createsource/drain regions 16. Often arsenic ions are used for thesource/drain implantation, at energy of about 50 keV to a dose of about3E15 per sq. cm. After removal of the photoresist, 18, about 500Angstrom of high temperature oxide (HTO) is formed and etched to createHTO spacers, 20. Next, about 1500 Angstroms of poly 3 is deposited andetched back to form poly plugs, 22, to contact the source drain regions,16. The structure is at this stage as depicted in FIGS. 1d and 2 d.Spacers 20 serve to isolate poly plugs, 22, from poly 1 regions, 8, andpoly 2 regions, 12. For this isolation to be reliable the spacers mustbe sufficiently wide, posing a restriction on shrinkage of the cell. Aphotoresist layer is formed and patterned, 24, to define the erasinggate regions. Poly 3 and poly 1 of the exposed regions are etched. Thestructure of the floating gates 30 is now complete. An implant, oftenBF2 at about 60 keV to a dose of about 1E13 per sq. cm., is performed toadjust the erasing gate threshold voltage and the exposed floating gateoxide, 6, is etched. At this point the structure is as depicted in FIGS.1e and 2 e. Following photoresist removal, about 250 Angstroms oferasing gate oxide, 26, is formed. Next the erasing gate, 28, is formed.This is accomplished by depositing about 1500 Angstroms of poly 4,forming and defining a photoresist layer for the erasing gate, etchingthe poly 4 and removing the photoresist. This completes the formation ofa traditional split gate flash memory cell, which is shown in FIGS. 1fand 2 f.

[0006] There are three basic operations used in a split gate flashmemory cell. These are the program operation, the erase operation andthe read operation, which are shown in FIGS. 3a and 3 b, FIGS. 4a and 4b, and FIGS. 5a and 5 b, respectively. In the programming operationelectrons are injected into a particular floating gate or bit, and theselection of the bit involves an erasing gate line acting as a word lineand a drain line acting as a bit line. The programming process, theprocess of charging the floating gates, is shown in FIG. 3a. Voltagesapplied to control gate, 36, erasing gate, 28, and transfer gate, 36,form an n-channel. The voltage applied to the drain, 32, is sufficientlyhigher than that applied to the source, 34, so that channel electrons inthe vicinity of the selected floating gate, 40, have been heatedsignificantly. A higher voltage applied to the control gate, 36, causesan enhanced injection of the heated electrons into the floating gate,40, which charges the floating gate. Selection of the programmed bit isillustrated in FIG. 3b. Successive erasing gate or word lines, 44, 28and 46 have 0, 2 and 0 volts applied respectively. Only with cell 40 arethe two necessary conditions for programming satisfied. It is along wordline 28 with 2 volts applied, so a continuous channel is establishedbetween source and drain so that channel electrons can be heated by thesource-drain potential difference. In addition, there is a highervoltage applied to its control gate to enhance injection of the heatedchannel electrons. Thus only bit 40 will be programmed. Other cells, 42,are not selected because either channel electrons are not heated, orthere is no higher voltage applied to a control gate to facilitateelectron injection into the corresponding floating gate or bothconditions are absent. In the erase operation, shown in FIGS. 4a and 4b, a high voltage, sufficient to cause Fowler-Nordheim (F-N) tunnelingthrough the poly-to-poly oxide between adjacent erasing and floatinggates, is applied to an erasing gate word line, 28. All other voltagesare maintained at 0 volts so that all floating gates along the biasedword line, 40 in FIG. 4b, are selected, while cells 42, along unbiasedword lines, such as 44 and 48, are not selected. The high erasing gatevoltage required, achieving sufficient F-N tunneling, could presentreliability issues due to high oxide stress. The read operation, inwhich the bit to be read is selected by a word line and a bit line, isshown in FIGS. 5a and 5 b and determines if the selected bit is in theprogrammed state or in the erased state. With the source, 34, at 0volts, 1.5 volts are applied to the drain line, 32, acting as the bitline, of the selected cell, 40, and 2 volts are applied to the erasinggate line, 28, acting as the word line of the selected cell, 40. Thereis 6 volts applied to transfer gates, 38 and 1.5 volts to control gates,36. When the selected cell is in the programmed state a channel does notform under the selected cell and the drain current is low. On the otherhand, when the selected cell is in the erased state a channel does formunder the selected cell and there is thus a complete channel from sourceto drain and a large drain current is observed.

[0007] A method of forming polysilicon gate tips for enhanced F-Ntunneling in split-gate flash memory cells is disclosed in U.S. Pat. No.6,117,733 to Sung et al. A method for shrinking array dimensions ofsplit-gate memory devices, using multilayer etching to define cell andsource lines, is disclosed in U.S. Pat. No. 6,207,503 to Hsieh et al. InU.S. Pat. No. 6,204,126 to Hsieh et al. there is disclosed a split-gateflash memory cell where the floating gate of the cell is self aligned toisolation, to source and to word line. In U.S. Pat. No. 6,228,695 toHsieh et al. there if disclosed a split-gate flash memory cell where thefloating gate of the cell is self aligned to the control gate and thesource is self aligned.

SUMMARY OF THE INVENTION

[0008] It is a primary objective of the invention to provide a method offorming self-aligned source and drain regions through which asignificant reduction in the split-gate flash memory cell area ispossible. As is well known in the art, a split-gate flash memory cellnormally has source and drain regions that are contacted by utilizingpoly plugs. Insulating layers are required as spacers to separate thesepoly plugs from the floating gates and control gates of the cell, andthis uses up area. Furthermore, because of the high voltages required inthe erase operation the spacer width cannot be decreased without payinga penalty in reduced reliability. Elimination of the poly plugs, as inthe method disclosed by the present invention, eliminates thereliability issue, allows a reduction in cell area and facilitatesshrinking the cell size. Instead of poly plugs, a new self-alignedsource/drain oxide etching procedure enables the formation ofsource/drain regions that are connected in rows directly within thesilicon. This procedure of connecting source/drains is generallyapplicable to arrays of MOSFET-like devices.

[0009] A new structure is disclosed for source/drain bit lines in arraysof MOSFET devices. Rows of conducting regions are formed by ionimplantation through openings adjacent to gate structures and inisolation regions separating columns of active areas of the arrays. Theopenings are filled with insulating material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawing forming a material part of thisdescription, there is shown:

[0011]FIGS. 1a-1 f show top views depicting a traditional method offorming split gate flash memory cells.

[0012]FIGS. 2a-2 f show cross sectional views depicting a traditionalmethod of forming split gate flash memory cells.

[0013]FIGS. 3a and 3 b show the program operation.

[0014]FIGS. 4a and 4 b show the erase operation.

[0015]FIGS. 5a and 5 b show the read operation.

[0016]FIGS. 6a-6 f show top views depicting a method of forming splitgate flash memory cells according to the invention.

[0017]FIGS. 7a-7 f show cross sectional views depicting a method offorming split gate flash memory cells according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Preferred embodiments of the invention are well described withthe aid of FIGS. 6a-6 f and 7 a-7 f. A method of fabricating a novelsplit gate flash memory cell is presented in FIGS. 6a-6 f, where topviews of the cell are presented at successive stages of the process andin FIGS. 7a-7 f; which show the corresponding cross-sections. Activeregions, 10, are defined on a p-type semiconductor substrate, 2, whichpreferably is a silicon substrate, using oxide filled isolation regions,such as shallow trench isolation, STI, regions, 4. An implant isperformed to adjust the cell threshold voltage, which may be a boronimplant at about 20 keV to a dose of about 5E11 per sq. cm. The floatinggate oxide, 6, is then formed to a thickness of about 150 Angstroms,followed by deposition of a conductive layer, which preferably is a poly1 layer, 8, to a depth of about 800 Angstroms. A photoresist layer isformed and patterned to partially define the poly 1 floating gates.After a poly 1 etch, to achieve the shape of region 8 as shown in FIG.6a, and removal of the photoresist, the structure is as depicted inFIGS. 6a and 7 a. As in the traditional method, the method of theinvention continues with formation of a dielectric separator between thepoly 1 floating gate and poly 2 control gate that is disposed over thedielectric separator. This dielectric separator often consists ofcomposite oxide/nitride/oxide (ONO) layers, with the layer thicknessbeing about 75, 150, 30 Angstroms, respectively. There follows adeposition of a conductive layer, which preferably is about 1000Angstroms of poly 2 and then deposition of about 1500 Angstroms ofnitride 1, which is preferably a silicon nitride layer. Two layers arenow applied that are required for the self-aligned source/drain etchingapproach of the invention. A deposition of about 500 Angstroms of aconductive layer, which is preferably a poly 3 layer, 50, is followed bydeposition of about 250 Angstroms of TEOS, 52, these layers serving asetch stop layers. A photoresist layer is formed and patterned to definethe control gates. Since in the self-aligned source/drain etchingapproach poly plugs are not needed to contact the source/drain regions,the source/drain openings 56 can be made much thinner than in thetraditional method. With no poly plugs in the source/drain openingsthere is no need of insulating spacers to isolate the poly plugs frompoly 1 and poly 2 regions, regions that could have sizable voltagesapplied. The only limitation is the required thickness of the sourcedrain regions. Thus, by eliminating the insulating spacers, substantialcell shrinkage is achieved. Etching the TEOS layer, the poly 3 layer,the nitride layer, the poly 2 layer and the ONO layer and then removingthe photoresist, results in the structure depicted in FIGS. 6b and 7 b.The ONO layer, 54, provides dielectric separation between the poly 2layer, 12, which acts as a control gate or transfer gate, and the poly 1floating gate. The nitride 1 layer, 14, is required for dielectricseparation between poly 2 and subsequent poly layers. A photoresistlayer is formed and patterned, 58, to define source/drain openings, poly1 is etched with the TAOS layer serving as an etching stop layer. Theself-aligned source/drain oxide etch step is now performed, removing thefloating gate oxide layers under poly 1 openings formed below thesource/drain openings 56 and also front STI regions along rows 60-60.Thus, the silicon surface is exposed continuously along rows 60-60.Source/drain implantation is now performed, and in addition to creatingsource/drain regions 16, the implantation also creates conductingregions, below the etched STI regions, that serve to electricallyconnect source/drain regions of a row. Common source/drain lines arethus formed, which are utilized as bit lines. Often arsenic ions areused for the source/drain implantation, at energy of about 50 keV to adose of about 3E15 per sq. cm. After removal of the photoresist, 58, alayer of high temperature oxide (HTO) is formed. The thickness of theHTO layer should be sufficient to fill the source/drain openings withoxide, 60 and also so that the sidewall spacers 20, created afteretching the HTO layer, are appropriately thick. A sidewall spacer isappropriately thick if, with voltage applied for an erase operation, thesidewall spacer is thin enough so that sufficient F-N current flowsthrough the spacer between the floating gate and erase gate, yet thickenough to avoid reliability concerns. The structure is at this stage asdepicted in FIGS. 6d and 7 d. Next a poly 1 etch completes thedefinition of the floating gates 62 and creates an opening for theerasing gates. At the same time the poly 3 layers are removed. Anerasing gate threshold voltage implant is performed, which commonly usesBF2 with an energy of about 60 keV to a dose of about 1E13 per sq. cm.,adjust the erasing gate threshold voltage and then the exposed floatinggate oxide, 6, is etched. At this point the structure is as depicted inFIGS. 6e and 7 e. About 250 Angstroms of erasing gate oxide, 66, isformed after which the erasing gate, 64, is formed. This is accomplishedby depositing about 1500 Angstroms of poly 4, forming and defining aphotoresist layer for the erasing gate, etching the poly 4 and removingthe photoresist. This completes the formation of a 1 split gate flashmemory cell according to the invention, which is shown in FIGS. 6f and 7f.

[0019] The three basic operations used in a split gate flash memoryaccording to the invention are exactly those used in conventional splitgate flash memories. These are the program operation, the eraseoperation and the read operation, which are shown in FIGS. 3a and 3 b,FIGS. 4a and 4 b, and FIGS. 5a and 5 b, respectively. In the programmingoperation electrons are injected into a particular floating gate or bit,and the selection of the bit involves an erasing gate line acting as aword line and a drain line acting as a bit line. The programmingprocess, the process of charging the floating gates, is shown in FIG.3a. Voltages applied to control gate, 36, erasing gate, 28, and transfergate, 36, form an n-channel. The voltage applied to the drain, 32, issufficiently higher than that applied to the source, 34, so that channelelectrons in the vicinity of the selected floating gate, 40, have beenheated significantly. A higher voltage applied to the control gate, 36,causes an enhanced injection of the heated electrons into the floatinggate, 40, which charges the floating gate. Selection of the programmedbit is illustrated in FIG. 3b. Successive erasing gate or word lines,44, 28 and 46 have 0, 2 and 0 volts applied respectively. Only with cell40 are the two necessary conditions for programming satisfied. It isalong word line 28 with 2 volts applied, so a continuous channel isestablished between source and drain so that channel electrons can beheated by the source-drain potential difference. In addition, there is ahigher voltage applied to its control gate to enhance injection of theheated channel electrons. Thus only bit 40 will be programmed. Othercells, 42, are not selected because either channel electrons are notheated, or there is no higher voltage applied to a control gate tofacilitate electron injection into the corresponding floating gate orboth conditions are absent. In the erase operation, shown in FIGS. 4aand 4 b, a high voltage, sufficient to cause Fowler-Nordheim (F-N)tunneling through the poly-to-poly oxide between adjacent erasing andfloating gates, is applied to an erasing gate word line, 28. All othervoltages are maintained at 0 volts so that all floating gates along thebiased word line, 40 in FIG. 4b, are selected, while cells 42, alongunbiased word lines, such as 44 and 48, are not selected. The higherasing gate voltage required, achieving sufficient F-N tunneling, couldpresent reliability issues due to high oxide stress. The read operation,in which the bit to be read is selected by a word line and a bit line,is shown in FIGS. 5a and 5 b and determines if the selected bit is inthe programmed state or in the erased state. With the source, 34, at 0volts, 1.5 volts are applied to the drain line, 32, acting as the bitline, of the selected cell, 40, and 2 volts are applied to the erasinggate line, 28, acting as the word line of the selected cell, 40. Thereis 6 volts applied to transfer gates, 38 and 1.5 volts to control gates,36. When the selected cell is in the programmed state a channel does notform under the selected cell and the drain current is low. On the otherhand, when the selected cell is in the erased state a channel does formunder the selected cell and there is thus a complete channel from sourceto drain and a large drain current is therefor observed. Processes toform the layers of embodiments of the invention, to etch or remove themand to perform the ion implantation steps are well known in detail bypractitioners of the art.

[0020] Other preferred embodiments of the invention could involve arraysof MOSFET devices other than split gate flash memory cells. Theobjective is to fabricate rows of electrically connected self-alignedsource/drain regions. In the method of the invention this isaccomplished after the layers comprising gate structures adjacent tosource/drains are formed. These layers are etched to the siliconsubstrate to form openings that are aligned in rows at source/drainpositions. At the same time opening are etched through to the siliconsurface of adjoining isolation regions aligned along the same rows asthe source/drain openings. Thus source/drain openings and isolationregion openings form continuous rows. Performing source/drain ionimplantation into the silicon under these openings creates continuousconductive regions forming rows through the silicon substrate underthese openings. Conductive regions under the source/drain openings actas source/drain regions and these are connected in rows by theconductive regions created under the isolation region openings. Theopenings can be filled with oxide, preferably high temperature oxide.Embodiments of the invention pertain to arrays of n-channel and arraysof p-channel MOSFET devices. For arrays of n-channel devices n-typeconductive regions are formed by ion implantation, by implanting arsenicions, for example. For arrays of p-channel devices p-type conductiveregions are formed by ion implantation, by implanting boron ions, forexample.

[0021] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetail may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A new structure for source/drain bit lines inarrays of MOSFET devices comprising: rows of conducting regions formedby ion implantation through openings adjacent to gate structures and inisolation regions separating columns of active areas of said arrays;said openings filled with insulating material.
 2. The structure of claim1 wherein said MOSFET devices are n-channel devices and said conductingregions are formed to be n-type.
 3. The structure of claim 1 whereinsaid MOSFET devices are p-channel devices and said conducting regionsare formed to be p-type.
 4. The structure of claim 1 wherein saidinsulating materials are oxide.
 5. The structure of claim 1 wherein saidinsulating materials are high temperature oxide.
 6. A method offabricating a new structure for source/drain bit lines in arrays ofMOSFET devices comprising: providing a partially processed array ofMOSFET devices having active areas arranged in columns which aresurrounded by insulator filled isolation regions and having formed, butnot patterned, all layers comprising gate structures that are adjacentto source/drain regions, etching, in rows, all layers comprising gatestructures that are adjacent to source/drain regions and insulatorfilled isolation regions to form openings that are aligned in rowspassing source/drain positions; performing ion implantation into thesilicon under said openings creating continuous conductive regionsforming rows through the silicon substrate under said openings. fillingsaid openings with insulating material.
 7. The method of claim 6 whereinsaid MOSFET devices are n-channel devices and said conducting regionsare formed to be n-type.
 8. The structure of claim 6 wherein said MOSFETdevices are p-channel devices and said conducting regions are formed tobe p-type.
 9. The structure of claim 6 wherein said insulating materialoxide.
 10. The structure of claim 6 wherein said insulating materialsare high temperature oxide.
 11. A method to fabricate self-alignedsource/chain lines in split gate flash memory arrays, comprising:providing an extensive p-type semiconductor region on a semiconductorsubstrate; defining columns of active regions by surrounding said activeregions with oxide filled isolation regions; performing a firstthreshold voltage adjust implant; forming a floating gate oxide layerover the surface of said active regions; forming a poly 1 layer; forminga photoresist layer and patterning said photoresist layer to etch saidpoly 1 layer so that after etching said poly 1 is disposed over saidactive regions; performing a poly 1 etch; removing the photoresistlayer; forming sequentially, a first insulating layer, a poly 2 layer, asecond insulating layer, a poly 3 layer and a first oxide layer; forminganother photoresist layer and patterning the photoresist to form, uponetching, two kinds of interposed openings in the row direction, i.e.,perpendicular to the active region columns; openings for source/drainlines that could be narrower than openings for erase gates; etchingsequentially, said first oxide layer, said poly 3 layer, said secondinsulating layer, said poly 2 layer and said first insulating layer;removing said other photoresist layer; forming a third photoresist layerand patterning the photoresist so as to deepen, upon etching, only theopenings for source/drain lines; etching poly 1; etching floating gateoxide and oxide of said isolation regions; performing a source/drain ionimplantation; removing the third photoresist layer; forming a secondoxide layer and etching said second oxide layer so that the source/drainopenings are filled with said second oxide and so that sidewall spacers,composed of said second oxide, remain, etching exposed poly 1 and poly3; performing a second threshold adjust implant for the erase gates;etching exposed floating gate oxide; forming an erasing gate oxidelayer; forming a poly 4 layer; forming a fourth photoresist layer andpatterning the photoresist for erase gate lines, in the columndirection, disposed over the active regions; etching poly 4; removingthe fourth photoresist layer.
 12. The method of claim 11 wherein saidp-type semiconductor region is a p-substrate.
 13. The method of claim 11wherein said p-type semiconductor region is a p-well.
 14. The method ofclaim 11 wherein said isolation regions are shallow trench isolationregions.
 15. The method of claim 11 wherein said first threshold voltageadjust implant is performed using Boron ions at energy of about 20 keVand a dose of about 5E11 per sq.cm.
 16. The method of claim 11 whereinsaid floating gate oxide is formed to a thickness of about 150Angstroms.
 17. The method of claim 11 wherein said poly 1 layer isformed to a thickness of about 800 Angstroms.
 18. The method of claim 11wherein said first insulating layer is an ONO layer in which the bottomoxide layer is about 75 Angstroms thick, the silicon nitride layer isabout 150 Angstroms thick and the top oxide layer is about 30 Angstromsthick.
 19. The method of claim 11 wherein said poly 2 layer is formed toa thickness of about 1000 Angstroms.
 20. The method of claim 11 whereinsaid second insulating layer is a silicon nitride layer that is about1500 Angstroms thick.
 21. The method of claim 11 wherein said poly 3layer is formed to a thickness of about 500 Angstroms.
 22. The method ofclaim 11 wherein said first oxide layer is a TEOS layer formed to athickness of about 250 Angstroms.
 23. The method of claim 11 whereinsaid source/drain openings are about 500 to about 2000 Angstroms wide.24. The method of claim 11 wherein said erase gate openings are about500 to about 2000 Angstroms wide.
 25. The method of claim 11 whereinsaid source/drain ion implantation is performed using Arsenic ions atenergy of about 50 keV and a dose of about 3E15 per sq.cm.
 26. Themethod of claim 11 wherein said second oxide layer is an HTO layerformed to a thickness of about 500 Angstroms.
 27. The method of claim 11wherein said second threshold voltage adjust implant is performed usingBF2 ions at energy of about 60 keV and a dose of about 1E13 per sq.cm.28. The method of claim 11 wherein said erase gate oxide is formed to athickness of about 250 Angstroms.
 29. The method of claim 11 whereinsaid poly 4 layer is formed to a thickness of about 1500 Angstroms.